1. Solving Maximum Clique Problems using FPGA Based on Swap-Based Tabu Search (2021)
2. Accelerating Swap-Based Tabu Search for Solving Maximum Clique Problems on FPGA 金澤 健治 ISPA-2019 (2019)
3. ``FPGA Acceleration to Solve Maximum Clique Problems Encoded into Partial MaxSAT'' Kenji Kanazawa, Shaowei Cai MCSoC-2018 217 - 224 (2018)
4. ``Acceleration of Solving Quadratic Assignment Problems on Programmable SoC using High Level Synthesis'' Kenji Kanazawa FSP-2017 40 - 47 (2017)
5. An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA Kenji Kanazawa, Tsutomu Maruyama E100D (8) 1807 - 1818 (2017)
6. ``FPGAを用いた画像処理応用のためのMonotone Chainアルゴリズムの高速計算'' 監物 香保里, 金澤 健治, 森 大和, 相部 範之, 安永 守利 電子情報通信学会論文誌 J100-D (1) 1 - 13 (2017)
7. High-speed calculation of convex hull in 2D images using FPGA Kenji Kanazawa, Kahori Kemmotsu, Yamato Mori, Noriyuki Aibe, Moritoshi Yasuanga 27 533 - 542 (2016)
8. An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search. Shohei Sassa, Kenji Kanazawa, Shaowei Cai, Moritoshi Yasunaga SIGARCH Computer Architecture News 44 (4) 32 - 37 (2016)
9. FPGA acceleration of SAT/Max-SAT solving using variable-way cache Kenji Kanazawa, Tsutomu Maruyama 1 - 4 (2014)
10. "Crosstalk-noise Reduction in GHz Domain Using Segmental Transmission Line" Katsuyuki Seki, Kenji Kanazawa, Moritoshi Yasunaga EDAPS-2013 1 - 4 (2013)

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